1. Technical Field of the Invention
The present invention relates to integrated circuits, and more specifically buried-gate semiconductor devices, that is, those in which at least a part of the gate region is placed under the channel region.
2. Description of Related Art
Among the so-called buried gate semiconductor devices, there are double planar gate devices, that is, devices in which the gate region comprises two gates, one of which is located above the channel region and the other of which is located below the channel region, and the so-called GAA (Gate All Around) devices, in which the gate region is formed by a single part and embeds the channel region.
The buried gate devices, whether double gate or not, are particularly advantageous for channel lengths of less than 50 nanometers, because they make it possib to eliminate the so-called short channel effects while making it possible to obtain a current intensity that is twice or three times that of a conventional transistor. It will be recalled here that a short channel presents a very small distance (length) between the source and the drain, and that the “short channel” effect is reflected in a lowering of the threshold voltage of the transistor, which can at the extreme limit result in a transistor being obtained that is very difficult to control, and culminate in the “piercing” mode.
The known buried gate devices comprise a gate produced from polysilicon. However, with the reduction of the dimensions for the next semiconductor devices, a polysilicon gate reveals numerous limitations such as polydepletion, an incompatibility with the high-permittivity dielectrics and an excessively high gate resistivity.
One solution is notably to use a metal gate, even if the setting of the threshold voltage of the device requires a metal for which the output work function can be modulated. An example of metal gate devices are the so-called TOSI (totally silicided) devices that are produced from a polysilicon gate on top of which is deposited a metal which diffuses into the polysilicon during an annealing. The siliciding is done vertically and at the end of the method of producing the semiconductor device.
In the case of buried gate devices, the metal is deposited on the lateral walls of the polysilicon forming the gate region or regions. However, a poor formation of the metal silicide is obtained, notably because of the limited diffusion length of the metal in the polysilicon.